Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system
US7257693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2004 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Oct 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache coherency rules for a multi-processor computing system that is capable of working with compressed cache lines' worth of information are described. A multi-processor computing system that is capable of working with compressed cache lines' worth of information is also described. The multi-processor computing system includes a plurality of hubs for communicating with various computing system components and for compressing/decompressing cache lines' worth of information. A processor that is capable of labeling cache lines' worth of information in accordance with the cache coherency rules is described. A processor that includes a hub as described above is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.