Method and system for designing a timing closure of an integrated circuit
US7257798B2 · kind B2 · utility
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1References
12Claims
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Key dates
| Filing date | Jun 21, 2005 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Jun 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between at least one pair of connected blocks depending upon a drive of a corresponding interconnect, the instantiation of the smallest repeater being based on pre-determined criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.