Patrick John Eichenseer
6Patents
3h-index
10Co-inventors
46Inventor score
Filing activity: Oct 22, 2001 → Oct 12, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6578183B2 | Method for generating a partitioned IC layout | Physics | 26 | Expired |
| US7603643B2 | Method and system for conducting design explorations of an integrated circuit | Physics | 9 | Active |
| US7155694B2 | Trial placement system with cloning | Physics | 3 | Expired |
| US8051397B2 | Method and system for conducting design explorations of an integrated circuit | Physics | 1 | Active |
| US7793254B2 | Method and system for designing a timing closure of an integrated circuit | Physics | 1 | Active |
| US7257798B2 | Method and system for designing a timing closure of an integrated circuit | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.