Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
US7258931B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2003 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Sep 5, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor wafers utilize asymmetric edge profiles (EP) to facilitate higher yield semiconductor device processing. These edge profiles are configured to reduce the volume of thin film residues that may form on a top surface of a semiconductor wafer at locations adjacent a peripheral edge thereof. These edges profiles are also configured to inhibit redeposition of residue particulates on the top surfaces of the wafers during semiconductor processing steps. Such steps may include surface cleaning and rinsing steps that may include passing a cleaning or rinsing solution across a wafer or batch of wafers that are held by a cartridge and submerged in the solution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.