Integrated circuit, its fabrication process and memory cell incorporating such a circuit
US7259414B2 · kind B2 · utility
0Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2002 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Sep 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
This integrated circuit comprises a capacitor (23) formed above a substrate (1) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure (7) for connection to the capacitor.The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.