Damascene interconnect structure with cap layer
US7259463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2004 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Apr 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.