Arrangement and method for digital delay line
US7259634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2004 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Jun 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An arrangement (100) and method for a high precision and low distortion digital delay line with infinite delay. The digital delay line has an oscillating ring (110) with an odd number of inverting elements that triggers a counter (120). A comparator (130) compares the counter and the MSB of a given delay word. A line of inverters (150–159), double the odd number in the ring oscillator, is connected to a MUX (160) controlled by the LSB of the delay word.This provides the advantages of: high resolution due to use of a small, basic component, self-delay ring oscillator; small silicon area due to use of a special decoding scheme use the rings number to produce large delays; and easy implementation as a digital block in an integrated circuit using a standard cells library to build the ring and the decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.