Semiconductor memory device with a memory cell array formed on a semiconductor substrate
US7259992B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 2005 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Nov 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array on a region of a substrate, the cell array having word lines, bit lines and memory cells at crossings between the word and bit lines, drain and source of each memory cell coupled to a bit line and source line, respectively; and a sense amplifier circuit reading data of selected memory cells. The device has a data read mode detecting whether cell current flows from a bit line to the source line in accordance with data of a memory cell under the condition the well region is set at a base potential; a selected word line is applied with a read voltage, which turns on or off the memory cell in accordance with data thereof; the source line is applied with a first voltage higher than the base potential; and the selected bit line is applied with a second voltage higher than the first voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.