Reference scheme for a non-volatile semiconductor memory device
US7259993B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 3, 2005 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Jun 17, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device is provided comprising a memory area and a circuitry area. The memory area includes a plurality of memory cells and a set of array reference cells that are programmable to have a threshold voltage corresponding to an erased or a programmed state of a memory cell. In the circuitry area, additional main reference cells are provided, which are configured to also have a threshold voltage corresponding to an erased or programmed state of a memory cell. The main reference cells are used for setting of said array reference cells and said array reference cells are provided as a reference for reading or writing a state of said memory cells. A method is also provided for setting array reference cells in a non-volatile semiconductor memory device to a predefined threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.