Method and circuit for transmitting data between systems having different clock speeds
US7260734B2 · kind B2 · utility
27Cited by
16References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2002 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Aug 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In order to carry out an equidistant data transfer between clock domains having different clock rates, a combination of a counter (1) and a finite state machine (2) is proposed. Said counter (1) continuously counts off the clock cycles of the faster clock (CLK2, while the finite state machine (2) monitors the clock edges of the slower clock (CLK1) and an enabling signal (EN) for the data transfer with the faster clock (CLK2) is produced according to the count of the counter (1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.