Method of forming a wear-resistant dielectric layer
US7262078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/04953
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate is provided. The substrate includes a plurality of devices disposed in the substrate, a plurality of contact pads disposed on a surface of the substrate and electrically connected to the devices, and a surface dielectric layer positioned on the surface of the substrate. Thereafter, a surface treatment process including at least a plasma etching process is performed. Subsequently, at least a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a dielectric layer on a surface dielectric layer. The PECVD process is performed in a high frequency/low frequency alternating manner. Following that, a masking pattern on the dielectric layer is formed, and an anisotropic etching process is carried out to form a plurality of openings corresponding to the contact pads in the dielectric layer. The openings expose the contact pads, and each opening has an outwardly-inclined sidewall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.