Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture
US7262082B1 · kind B1 · utility
98Cited by
172References
200Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 3, 2006 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Aug 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a three-dimensional stacked semiconductor package includes providing a first semiconductor chip assembly that includes a first chip, a first conductive trace and a first encapsulant, wherein the first conductive trace includes a first metal pillar, providing a second semiconductor chip assembly that includes a second chip, a second conductive trace and a second encapsulant, wherein the second encapsulant includes a second aperture, and then positioning the first and second assemblies such that the first assembly overlaps the second assembly and the first metal pillar extends into the second aperture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.