Method of providing an interface to a plurality of peripheral devices using bus adapter chips
US7263570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2006 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | May 3, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.