Methods and apparatus for power control in a scalable array of processor elements
US7263624B2 · kind B2 · utility
42Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | May 13, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Dec 9, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.