Method for fabricating field-effect transistor structures with gate electrodes with a metal layer

US7265007B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Johann Harter · Dresden, DE
• Thomas Schuster · Ottenbach, DE

Key dates

• Filing date: Jun 27, 2005
• Grant date: Sep 4, 2007
• Expiry date: Sep 13, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/28247
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Provided is a method for fabricating gate electrode structures each having at least one individual polysilicon layer and a metal layer. A polysilicon layer is provided and patterned prior to the application of the gate metal. Trenches between the resulting gate structures are filled, and the polysilicon is drawn back to below the top edge of the fillings. The relief formed from the fillings and the polysilicon which has been caused to recede forms a shape which is used to pattern the gate metal without a lithographic step. The provision of a gate sacrificial layer, which is patterned together with the polysilicon layer, makes it possible to form contact structures from a contact metal prior to the application of the gate metal.