High performance vertical PNP transistor method
US7265010B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Jun 8, 2004 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Feb 28, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/969
Abstract
The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.