Method of manufacturing a transistor
US7265011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2004 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Mar 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0217
Abstract
A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.