Method for filling trench and relief geometries in semiconductor structures

US7265025B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dietmar Temmler · Dresden, DE
• Barbara Lorenz · Dresden, DE
• Daniel Koehler · Althengstett, DE
• Matthias Foerster · Dresden, DE

Key dates

• Filing date: Dec 10, 2004
• Grant date: Sep 4, 2007
• Expiry date: Nov 17, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/712
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.