Method and structure for composite trench fill
US7265398B1 · kind B1 · utility
7Cited by
13References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2004 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Apr 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/763
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combination of oxide and polysilicon are used to fabricate a composite trench fill. The trench bottom and a lower portion of the walls are covered with oxide. The remaining portion of the trench volume is filled with polysilicon. The method may be used for junction field effect transistors (JFETs) and metal oxide semiconductor field effect transistors (MOSFETs).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.