Embedded channel adapter having link layer configured for concurrent retrieval of payload data during packet transmission
US7266614B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Sep 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An host channel adapter embedded within a processor device includes a transport layer module, a transport layer buffer, a link layer module, and a link layer buffer configured for storing at least two packets to be transmitted by the embedded host channel adapter. The transport layer module is configured for generating, for each packet to be transmitted, a transport layer header, and storing in the transport layer buffer the transport layer header and a corresponding identifier that specifies a stored location of a payload for the transport layer header. The link layer module includes payload fetch logic configured for fetching the payload based on the corresponding identifier, enabling the link layer module to construct one of the two packets to be transmitted concurrently during transmission of the second of the two packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.