Programmable scan shift speed control for LBIST
US7266745B2 · kind B2 · utility
8Cited by
14References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 2, 2005 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Nov 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where scan shift operations of the LBIST circuitry are performed at reduced rates. In one embodiment, a base clock signal is gated before being provided to LBIST circuitry. The clock signal is gated to produce an effective clock rate that is reduced in one or more steps from a first rate that is used in a functional phase of LBIST testing to a reduced rate that is used in a scan shift phase. The effective clock rate is stepped back up at the end of the scan shift phase to the first rate which is used in the following functional phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.