Pipelined architecture implementing recursion processes for forward error correction
US7266757B1 · kind B1 · utility
8Cited by
2References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2004 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Oct 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3972
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing a recursion process on a data block for error correction. The disclosure describes concurrently operating pipelined sub-processes that decode the data block with error correction. The pipelined sub-processes are implemented as sub-circuits of an integrated circuit. The output data from each sub-process is stored for input by a subsequent sub-process of the pipelined sub-processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.