Semiconductor integrated circuit device and error checking and correcting method thereof
US7266759B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Aug 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.