Method for optimising transistor performance in integrated circuits
US7266787B2 · kind B2 · utility
95Cited by
5References
38Claims
0Family size
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Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Oct 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.