Icera, Inc.
91Patents
84Active
91Granted
54Portfolio score
Filing activity: Mar 31, 2004 → May 11, 2017 · 55 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8193044B2 | Memory cells | Electricity | 215 | Active |
| US7266787B2 | Method for optimising transistor performance in integrated circuits | Electricity | 95 | Expired |
| USD764033S1 | Toilet | General | 27 | Active |
| US7933405B2 | Data access and permute unit | Physics | 25 | Active |
| US7996581B2 | DMA engine | Physics | 22 | Active |
| US7564274B2 | Detecting excess current leakage of a CMOS device | Electricity | 17 | Expired |
| USD807480S1 | Toilet | General | 14 | Active |
| USD807479S1 | Toilet | General | 12 | Active |
| US7454684B2 | Apparatus and method for turbo decoder termination | Electricity | 9 | Expired |
| US7996711B2 | Memory errors | Physics | 8 | Active |
| US7424071B2 | Decoder and a method for determining a decoding reliability indicator | Electricity | 7 | Active |
| US8836434B2 | Method and system for calibrating a frequency synthesizer | Electricity | 7 | Active |
| US8024557B2 | Booting an integrated circuit | Physics | 6 | Active |
| US8189653B2 | Radio receiver in a wireless communications system | Electricity | 5 | Active |
| US8493136B2 | Driver circuit and a mixer circuit receiving a signal from the driver circuit | Electricity | 5 | Active |
| US8384457B2 | Duty cycle correction | Electricity | 5 | Active |
| US7583106B2 | Clock circuitry | Physics | 5 | Active |
| US7287237B2 | Aligned logic cell grid and interconnect routing architecture | Physics | 5 | Expired |
| US8484442B2 | Apparatus and method for control processing in dual path processor | Physics | 4 | Active |
| US9047094B2 | Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor | Physics | 4 | Active |
| US7880500B2 | Logical signal voltage converter | Electricity | 4 | Active |
| US7949856B2 | Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit | Physics | 4 | Expired |
| US8527671B2 | DMA engine | Physics | 3 | Active |
| US8577304B2 | Synchronous CDMA communication system | Electricity | 3 | Active |
| US8782376B2 | Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.