Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US7268024B2 · kind B2 · utility
69Cited by
88References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 29, 2004 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Nov 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.