Methods of manufacturing metal-silicide features
US7268065B2 · kind B2 · utility
10Cited by
13References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2004 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jun 17, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.