Enhanced PMOS via transverse stress
US7268399B2 · kind B2 · utility
3Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2004 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Aug 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.