Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip
US7268570B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2006 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jun 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2855
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.