Adder circuitry for a programmable logic device
US7268584B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Nov 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5055
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLD having logic blocks capable of performing addition with a constant and non-constant value where the constant value is provided directly to an adder, without first passing it through a look up table. The PLD includes a plurality of logic blocks arranged in a two dimensional array. Row and column interconnects are provided to interconnect the plurality of logic blocks arranged in the two dimensional array. The plurality of logic blocks each include a look up table configurable to perform combinational logic and an adder circuit configured to perform adding functions. Each logic block also includes circuitry configured to directly provide a constant value to the adder circuit without passing the constant value through the look up table. The look up table is therefore available to perform other logic functions that would otherwise have to performed elsewhere on the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.