Nonvolatile phase change memory device and biasing method therefor
US7269080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Aug 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arranged on the same column; a row decoder coupled to the memory array to bias the word lines; a column decoder coupled to the memory array to bias the bit lines; and a biasing circuit coupled to the row decoder and to the column decoder to supply a first biasing voltage and a second biasing voltage to the terminals of an addressed memory cell, wherein the first biasing voltage is a positive biasing voltage and the second biasing voltage is a negative biasing voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.