Divisible true dual port memory system supporting simple dual port memory subsystems
US7269089B1 · kind B1 · utility
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3References
19Claims
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Key dates
| Filing date | Aug 8, 2006 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Aug 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory circuit and a method for configuring the same. The circuit includes a first array of memory cells including a first plurality of ports and a second plurality of ports, and a second array of memory cells including a third plurality of ports and a fourth plurality of ports. Additionally, the circuit includes a plurality of switches connected to the first plurality of ports and the third plurality of ports respectively or connected to the second plurality of ports and the fourth plurality of ports respectively. Moreover, the circuit includes a plurality of sense amplifiers and a plurality of write drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.