Low-latency equalization in multi-level, multi-line communication systems
US7269212B1 · kind B1 · utility
250Cited by
166References
29Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 5, 2000 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Nov 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03477
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Low-latency equalization mechanisms for multi-PAM communication systems are disclosed that reduce delay and complexity in signal correction mechanisms. The equalization mechanisms tap into input signals for a multi-PAM signal driver, and compensate for attenuation along a signal transmission line, crosstalk between adjacent lines, and signal reflections due to impedance discontinuities along the line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.