Jun Kim
50Patents
12h-index
55Co-inventors
87Inventor score
Filing activity: Feb 6, 1997 → Apr 15, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6643787B1 | Bus system optimization | Electricity | 313 | Expired |
| US6125157A | Delay-locked loop circuitry for clock delay adjustment | Electricity | 250 | Expired |
| US7269212B1 | Low-latency equalization in multi-level, multi-line communication systems | Electricity | 250 | Expired |
| US6539072B1 | Delay locked loop circuitry for clock delay adjustment | Electricity | 169 | Expired |
| US6950956B2 | Integrated circuit with timing adjustment mechanism and method | Electricity | 132 | Expired |
| US5945862A | Circuitry for the delay adjustment of a clock signal | Electricity | 89 | Expired |
| US7254075B2 | Integrated circuit memory system having dynamic memory bank count and page size | Physics | 86 | Expired |
| US7042914B2 | Calibrated data communication system and method | Electricity | 77 | Expired |
| US6163178A | Impedance controlled output driver | Electricity | 62 | Expired |
| US7535933B2 | Calibrated data communication system and method | Electricity | 53 | Active |
| US6661268B2 | Charge compensation control circuit and method for use with output driver | Electricity | 24 | Expired |
| US7039147B2 | Delay locked loop circuitry for clock delay adjustment | Electricity | 18 | Expired |
| US7755968B2 | Integrated circuit memory device having dynamic memory bank count and page size | Physics | 12 | Active |
| US6987823B1 | System and method for aligning internal transmit and receive clocks | Electricity | 11 | Expired |
| US7091761B2 | Impedance controlled output driver | Electricity | 11 | Expired |
| US8170067B2 | Memory system with calibrated data communication | Electricity | 11 | Active |
| US7308065B2 | Delay locked loop circuitry for clock delay adjustment | Electricity | 9 | Expired |
| US6342800B1 | Charge compensation control circuit and method for use with output driver | Electricity | 9 | Expired |
| US9785589B2 | Memory controller that calibrates a transmit timing offset | Electricity | 7 | Active |
| US9515204B2 | Synchronous wired-or ACK status for memory with variable write latency | Emerging Cross-Sectional Technologies | 5 | Active |
| US9235537B2 | Drift detection in timing signal forwarded from memory controller to memory device | Emerging Cross-Sectional Technologies | 5 | Active |
| US6922092B2 | Impedance controlled output driver | Electricity | 5 | Expired |
| US10446570B2 | Semiconductor memory device | Electricity | 4 | Active |
| US9164933B2 | Memory system with calibrated data communication | Electricity | 3 | Active |
| US9568942B2 | Drift adjustment in timing signal forwarded from memory controller to memory device based on a detected phase delay occurring on a second timing signal with a different frequency | Emerging Cross-Sectional Technologies | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.