Method for producing chip stacks and chip stacks formed by integrated devices
US7271026B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2005 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Jun 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06575
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated structure on a single substrate, an area of the first integrated structure and an area of the second integrated structure adjoining a respective first and second kerf area; providing a first redistribution layer on the first integrated structure on the substrate, said first redistribution layer at least partially extending beyond the area of the first integrated structure into the first kerf area, thereby forming a first integrated device area, wherein a first contact pad is arranged on the first redistribution layer in a first contacting area overlapping the first kerf area; providing a second redistribution layer on a second integrated structure on the substrate, including a second contact pad, thereby forming a second integrated device area; separating the first and second integrated device areas along a separation line defined by at least one of the boundaries of the first integrated device area and the second integrated device area, resulting in separated first and second integrated devices; and stacking the second in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.