Low-power receiver equalization in a clocked sense amplifier
US7271623B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver includes clocked, differential equalization circuitry to compensate for signal attenuation that varies with the frequency of the input signal received over a respective communication channel. The incoming signal is split into filtered and unfiltered signal components. Separate current-steering transistors coupled in parallel amplify the filtered and unfiltered components and sum the results. The filter or filters used to separate the signal components may be tunable, e.g. using voltage-controlled filter components. The ratio of device sizes for the current-steering transistors sets the magnitude of the boost applied to high-frequency components. The embodiments include adjustable or programmable current-steering networks to facilitate adjustments that accommodate the unique characteristics of individual communication channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.