Error detection during processor idle cycles
US7272751B2 · kind B2 · utility
4Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2004 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Jun 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, system, and signal-bearing medium that in an embodiment detect an event that will cause idle cycles in the processor and issue diagnostic instructions to the processor during the cycles that would be idle. In another embodiment, the processor is periodically interrupted and diagnostic instructions are issued to the processor, where the diagnostic instructions are selected based on a history of activity at the processor and a log of previous errors at the processor. In this way, errors may be detected at the processor without undue cost and impact on performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.