Field effect transistor (FET) having wire channels and method of fabricating the same
US7274051B2 · kind B2 · utility
31Cited by
6References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2005 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Mar 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
Abstract
In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns and at least two rows, and a gate dielectric layer surrounding each of the plurality of wire channels and a gate electrode surrounding the gate dielectric layer and each of the plurality of wire channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.