Nonvolatile semiconductor memory device having pair of selection transistors with different source and drain impurity concentrations and with different channel dopant concentrations
US7274075B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2006 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Oct 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetical to the shape of the drain diffusion layer region thereof below the selection gate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.