Storage device and control method therefor
US7274602B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 2006 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | May 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The conductance of a first switch circuit (T1) is periodically controlled in response to an error-amplification circuit (A1) whereby electric power, stored in an inductance circuit (L1) from INPUT VOLTAGE VIN, is released, through a rectifier circuit (D1), to a memory cell array (11) for providing BIAS VOLTAGE VPP stepped up to a set voltage value. At this time, a voltage regulating section (13) acts on the error-amplification circuit (A1) of the stepped up voltage supplying section (12) in response to LOCATIONAL INFORMATION AD about a memory cell as a voltage application target of BIAS VOLTAGE VPP and COUNTER INFORMATION COUNT, and directly regulates the voltage value of BIAS VOLTAGE VPP. Even for large storage capacity devices, it is possible to supply a bias voltage stepped up with a sufficient supply capability to the memory cell array (11). It is also possible to supply an optimum stepped up bias voltage by regulation of the set voltage depending on the position of a target memory cell, regardless of the number of target memory cells and their position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.