Handling of the transmit enable signal in a dynamic random access memory controller
US7275137B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2004 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Nov 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, an apparatus, and a computer program are provided for controlling a transmission enable (TX_ENA) signal. In Extreme Data Rate (XDR™) Dynamic Random Access Memories (DRAMs) or XDRAMS, there is a requirement that a TX_ENA signal remain logic high for a few cycles before data transmission, and, when TX_ENA transitions to logic low, TX_ENA remain logic low for a few cycles. However, maintaining this timing can be difficult with back-to-back writes. Therefore, additional logic is employed within XDRAM memory controllers to insure that TX_ENA does not violate system requirements by allowing TX_ENA to remain logic high between successive writes or when the system is devoid of commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.