Method of embedding passive component within via
US7275316B2 · kind B2 · utility
8Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2004 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Mar 31, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.