Method of manufacturing a passive integrated matching network for power amplifiers
US7276420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2005 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Mar 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.