Designs and methods for conductive bumps
US7276801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2003 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Sep 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3651
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.