Clock signal generation using digital frequency synthesizer
US7276952B2 · kind B2 · utility
5Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2005 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Oct 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of generating a clock signal using a digital frequency synthesizer includes providing a base clock to the digital frequency synthesizer, comparing a phase of an output clock from the digital frequency synthesizer with a phase of a reference signal, and issuing at least one frequency control command to the digital frequency synthesizer to align the phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.