Memory module with a defective memory chip having defective blocks disabled by non-multiplexed address lines to the defective chip
US7277337B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2006 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Sep 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A downgraded memory module has downgraded DRAM chips soldered to its substrate. The downgraded DRAM chips have a defective memory cell in a logical quadrant of the memory. A physical MSB is a row address present on a non-downgraded DRAM of size S but not used on a downgraded DRAM size S/2. The physical MSB and a second address pin are non-multiplexed address pins that do not carry column addresses. The physical MSB and the second address pin logically divided the DRAM into quadrants. Two good quadrants without defects are selected, and jumpers on the memory module drive the physical MSB and the second address pin with signals that select only these two quadrants and disable access to quadrants containing defects. DRAM chips can be marked or sorted into bins for combinations of good quadrants. Downgraded memory modules have all DRAM chips from the same bin that share jumper settings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.