On chip network
US7277449B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | May 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/102
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address. The arbiter receives transaction requests, arbitrates among transaction requests, provides acknowledgements and controls the interconnect to select data paths between sources and destinations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.