De-packaging process for small outline transistor packages
US7279343B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Apr 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73265
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to de-packaging a semiconductor device to access and test the die within the package. The method involves initially removing molding compound from a first surface of the package to expose the underlying die attach pad of the package. A mask is then formed over the die attach-pad. An etching solution is subsequently introduced through an opening in the mask to etch away the die attach pad. Once the etching is complete, the die attach film is removed. An ohmic contact is then formed on the exposed back surface of the die. The ohmic contact is used to ground the die so that the electrical circuitry on the device will operate properly. Once grounded, the circuitry on the die can be electrically tested and debugged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.