Method of manufacturing a vertical junction field effect transistor having an epitaxial gate
US7279368B2 · kind B2 · utility
11Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Mar 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
Abstract
A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is formed within the trench by epitaxial regrowth. The epitaxial gate structure may include separate first and second epitaxial gate layers, and may have either a graded or uniform dopant concentration profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.