SRAM cell with improved layout designs
US7279755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Mar 31, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled between the supply source and the complementary supply source. The cell further includes a first pass-gate and second pass-gate transistors coupled to the first and second inverters, respectively. The first pass-gate transistor and the first pull-up transistor are respectively constructed on a first P-type well and a first N-type well adjacent to one another, which are overlaid by a first doped region and a second doped region of substantially the same width in alignment with one another, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.